Integrated circuit protected against electrostatic discharges, with variable protection threshold

ABSTRACT

To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

This application is a continuation of application Ser. No. 08/320,124filed Oct. 7, 1994, now abandoned, which is a continuation ofapplication Ser. No. 08/149,719 filed Nov. 9, 1993, now abandoned, whichis a continuation of application Ser. No. 07/814,400 filed Dec. 23,1991, now abandoned, which is a Reissue of 07/264,202, now U.S. Pat. No.4,890,187 filed Oct. 28, 1988.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention concerns integrated circuits made with MOS(metal-oxide-semiconductor) technology and, more generally, integratedcircuits susceptible to risks of malfunctioning or destruction in thepresence of electrostatic discharges.

Electrostatic discharges may sometimes occur quite simply because a usertouches the input/output terminals of the integrated circuits. This riskwill become increasingly frequent as integrated circuits come intowidespread use among the public, for example in the form of chip cardswhich will undergo a lot of handling and in which the output terminalcan be directly accessed without protection.

2. Description of the Prior Art

To protect integrated circuits against these risks, it is now standardpractice to provide for an element integrated in the circuit, betweeneach of the signal terminals and the common ground terminal. Thefunction of this element is to become suddenly conductive whenovervoltage, exceeding a pre-defined threshold, appears between itsterminals. This element, of course, has energy absorption or currentabsorption capacities which are greater than those of the other elementsof the integrated circuit and, furthermore, it is designed to becomeconductive more quickly than the elements to be protected in theintegrated circuit.

In a standard way, the protection element is a diode with its anodeconnected to the ground terminal and its cathode connected to anotherinput/output terminal (assuming, of course, that the ground terminal isa negative supply terminal).

This diode stays normally off for as long as the voltage of the terminalto be protected does not go beyond an avalanche threshold. If thethreshold is exceeded, the diode goes into avalanche mode and absorbsthe electrostatic discharge current. It must go into avalanche modebefore the other junctions, present in the integrated circuit andsubject to the same overvoltage. Now, the voltage for triggering theavalanche process is essentially related to technological parameterssuch as the doping of the semiconducting substrate in which the circuitis formed, and the doping of the various regions diffused in thissubstrate.

It is difficult to have precise knowledge of the avalanche voltages ofthe junctions to be protected and to master the making of a protectivediode with an avalanche voltage which would be below that of thejunctions to be protected while, at the same time, remaining greaterthan the normal operating voltages of the circuit. For, it would beunacceptable for the protection element to go into a conduction statesimply because a signal which has a relatively wide amplitude (but doesnot represent a dangerous discharge) appears at a terminal of thecircuit.

Now, the specifications relating to behaviour, under voltage, of theintegrated circuits are relatively strict and are finally fairly closeto voltages which might damage or destroy the circuit. For example,specifications may require that the circuit should work normally if itreceives signals or supply voltages of up to 15 volts, whereas thedestruction threshold would be 22 volts. It must therefore be seen to itthat the triggering of the protective element starts from a voltagewhich is considerably below 22 volts (if it is too close to 22 volts,there remains a risk of destruction because the conduction is nottriggered fast enough). But it is also necessary that the protectionelement should be triggered for a voltage which is sufficiently greaterthan 15 volts (if not, there is a risk of untimely triggering below 15volts).

The margin available for choosing the avalanche voltage is thereforenarrow and it is all the smaller as technological variations aregreater, i.e. it is all the smaller as the dimensions, concentrations,depths of junctions and other parameters are less well controlled in themanufacturing process.

To arrive at protection of the integrated circuits which is as efficientas possible while, at the same time, permitting normal functioningvoltages which are as high as possible, the present invention proposes anew approach based on the observation that the rising edge of theovervoltages coming from electrostatic discharges (or of mostovervoltages liable to appear and damage the circuits) is far steeperthan the rising edge of the normal voltages (which may be relativelyhigh) occurring at the input/output terminals of the circuit.

For, these normal voltages are either supply voltages which may exceedthe value stipulated by the specifications but for which there is noreason or possibility that they should vary abruptly, or input-outputlogic signals which would exceptionally change to a value greater thanthe maximum permitted by the specifications. The rising edges of theselogic signals do not exceed a few volts per nanosecond, while the risingedges of the electrostatic discharges rather have values of a somehundreds of volts per nanosecond.

SUMMARY OF THE INVENTION

According to the invention, it is proposed to connect, between twoterminals of the integrated circuit, a diode associated with a means tomodify the distribution of the equipotential lines at the position wherethe avalanche conduction of the diode is triggered, said means beingconnected to the terminal to be protected and being sensitive to therising slope of the overvoltages appearing at this terminal in such away that the avalanche triggering voltage is weaker, when the slope issteeper, than it is when the slope is less steep.

The means for modifying the distribution of equipotential lines ispreferably an insulated gate surrounding an entire diffused regionconstituting the cathode (or anode) of the diode, and located in theimmediate vicinity of this region.

This gate is connected to the terminal to be protected by an integratingcircuit that introduces a time constant in such a way that anovervoltage with a steep edge reaching this terminal is transmitted witha slight delay to the gate.

For example, the gate is connected, firstly, to one end of a resistor,the other end of which is connected to the diffused region and theterminal to be protected and, secondly, to an end of a capacitor, theother end of which is connected to the other terminal of the diode.

In practice, the capacitor does not need to be given the form of a wellidentified circuit element, for the junction capacitances of theresistor (made by a diffused region in the substrate) and thecapacitance between the gate and the semiconducting substrate in whichthe cathode of the diode is diffused are high enough to play the roleexpected of them, namely to cause a delay in the arrival of a voltagefront at the gate. This delay induces a potential difference between thediffused region and the gate, which is all the greater as the front issteeper.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention will appear from thefollowing detailed description made with reference to the appendeddrawings, of which:

FIG. 1 gives a schematic view of an integrated circuit, one inputterminal of which is protected by a protection element.

FIG. 2 gives a symbolic view of the protection device according to theinvention,

FIG. 3 shows a lateral sectional view, along the line AA of FIG. 4, of apossible structure for the protection element according to theinvention,

FIG. 4 shows a top view of the structure of FIG. 3 also showing theconstitution of the integration resistor of FIG. 2.

DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1 gives a schematic view of an integrated circuit CI, with twoinput/output terminals M and B. Of course, the circuit may have otherterminals which have not been shown.

The terminal M is a potential reference terminal. It is the mostnegative or the most positive terminal of the circuit. In the examplewhich shall be described in the rest of the description, it is the mostnegative terminal, that is to say, in normal operation, the voltage atthe terminal B never goes below the potential of the terminal M.

The terminal B is an input/output terminal to be protected. It may be asignal terminal receiving logic signals, or again, a positive supplyterminal.

In a standard way, there is provision for a protection element P betweenthe terminals B and M. This element behaves like a practically infiniteimpedance for as long as the potential difference between the terminalsB and M does not exceed a threshold Vs, and then as a voltage limiterwith a high current absorption capacity when this threshold is exceeded.

The invention concerns the formation of the protection element.

FIG. 2 gives a schematic view, in symbolic form, of the operatingprinciple of the protection element according to the invention, placedbetween the terminals B and M of the integrated circuit.

The protection element behaves, firstly, like a diode D, the anode ofwhich is connected to the terminal M and the cathode to the terminal B.This diode is normally reverse biased since, as stated, the potentialspresent at the terminal B are greater than the reference potential M. Inany case, if the potential of the terminal B drops by about 0.6 voltsbelow the reference voltage, the diode would start conducting,preventing this fall from continuing.

When the potential of the terminal B becomes highly positive and exceedsa certain threshold Vs, the reverse biased diode D goes into theavalanche state and starts conducting.

In FIG. 2, a symbolic depiction is given, in the form of a gate G in thevicinity of the junction of the diode D, of a means to cause variationin the threshold Vs for which the diode D goes into avalanche mode. Theapplication to the gate G of a variable potential Vg has the effect ofmodifying the threshold Vs.

More precisely, depending on the aim sought to be achieved according tothe invention, namely the increasing of Vs if the overvoltages aresimply “normal” level signals, which are slightly too high and thereducing of Vs if the overvoltages are of electrostatic origin, the gateG is connected to the terminal B by means of an integrating circuit insuch a way that the potential Vg follows the potential of the terminal Bwith a certain delay. This circuit acts in such a way that the potentialVg remains all the closer to the potential of the terminal B as therising time of the overvoltages applied to the terminal B are slowerduring the rising of the signal.

The integrating circuit is shown in the form of a resistor R and acapacitor C. The resistor R is connected between the gate and theterminal B. The capacitor C is connected between the gate G and theground M.

The gate is placed in the vicinity of the junction of the diode D insuch a way that it has an influence on the distribution of theequipotential lines inside the anode regions and cathode regions of thediode. This influence is in the following direction: the equipotentiallines are more curved and more contracted in the breakdown region of thediode (the region in which the avalanche mode gets initially triggered)when the potential Vg is weaker. They are less curved and more spacedout when the potential Vg is greater.

The result of this is that the breakdown occurs for a higher voltage Vs1when there is an overvoltage with a relatively slow rising edge and alower voltage Vs2 when there is an overvoltage with a very steep risingedge. In both cases, the gate potential Vg ad the potential of theovervoltage on the terminal B rise and equipotential lines increasetheir curvature and get contracted as and when this rise occurs. But, inthe latter case, the gate potential Vg is not able to follow thepotential on the line B, and the curvature of the equipotential lines iseven greater and their contraction is even greater than in the formercase during the rising edge. The result of this is that the avalanchethreshold is appreciably lower in the case of a very steep rising edge.

In an illustrative, digital example, it can be shown that with aresistance of 2 kilohms and a capacitance of 0.1 picofarad, thepotential Vg will follow the potential of the terminal B with adifference of about 1 volt for rising edges of about 5 volts pernanosecond (standard value for logic signals), and a difference veryswiftly reaching 40 volts for rising edges of 200 volts per nanosecond(standard value for electrostatic discharges). This difference betweenthe two cases is quite enough to substantially modify the avalanchevoltage threshold of the diode.

The invention can be implemented especially with a diffused junctiondiode flush with the surface of a semiconducting substrate, the surfaceoutcrop of the junction being surrounded by or covered with an insulatedconducting gate coming to the immediate vicinity of the junctionthroughout its periphery.

FIG. 3 shows a lateral cross-section view of a structure of this typeand FIG. 4 shows a top view. The section is made along the lines AA ofFIG. 4. In FIG. 4, the crosses show contact zones between a conductingmetallization and a sub-adjacent region.

The diode D consists of an N+ type region 12 diffused on the surface ofa P type semiconducting substrate 10.

The substrate is connected to the ground M either by its rear face or bymeans of a P+ type region 14, locally diffused at the surface of thesubstrate and covered with a metallization 16 which connects it with theterminal M.

The region 12 is connected to the terminal B by a metallization 18.

The region 12 is made by local diffusion of N+ type impurities from thesurface of the substrate. The junction between the region 12 and thesubstrate 10 thus has, as is well known, a curvature 20 along itsperiphery, where it rises towards the upper surface of the substrate.

It is known that it is in the region of this curvature 20 that theavalanche mode is initially triggered when the diode is subjected to ahigh reverse voltage. The reason for this is that the equipotentiallines are highly curved and contracted in the neighbourhood of thiscurvature.

Sometimes also, the avalanche mode is triggered in the zone where thejunction is flush with the surface of the substrate, either because thedopings are higher at the surface or as a result of faults that mightexist at the surface outcrop of the junction. In this case too, thebreakdown occurs in the zones where the electrical field is the highestwith respect to the capacity of these zones to support this electricalfield, and consequently, again in the zones where the equipotentiallines are the most contracted.

The periphery of the diffused region 12 is completely surrounded by apolycrystaline silicon gate G covering the outcrop of the junction andinsulated from the surface of the substrate by a thin insulating layer22 (silicon oxide). This gate G is made by the same process as the gatesof the MOS transistors of the integrated circuit and, similarly, as thegates of the MOS transistors that go slightly beyond the source anddrain regions. Similarly, the gate G covers the surface outcrop of thejunction in going very slightly beyond the entire periphery of theregion 12.

The greater the positive potential applied to the gate G, the more theequipotential lines in the neighbourhood of the curvature of thejunction 20 and the surface outcrop of the junction get loosened and,hence, the greater is the voltage Vs needed for application to theterminals of the diode D to put it in avalanche mode.

The general form of the equipotential lines in the presence of apositive voltage at the gate G is shown schematically by dashes in FIG.3. In the presence of a null potential at the gate G, the equipotentiallines remain practically parallel to the curvature 20 and rise to thesurface.

The gate G is connected to the terminal B by means of a resistor R whichcannot be seen in the section AA of FIG. 3 but is seen in the top viewof FIG. 4. This resistor can be made by a slightly doped N typediffusion 24 in the P type substrate. A metallization 26 (FIG. 4) comesinto contact in a region 28 with the gate G and, in a region 30, with anend of the diffusion 24. Another end of the diffusion 24 is connected bya contact zone 32 with the metallization 18, hence with the terminal B.The contacts 30 and 32 are formed on top of the small N+ type regions30′ and 32′ diffused at the ends of the resistor 24.

The capacitance value of C of the diagram of FIG. 2 is simply theexisting capacitance between the gate and the substrate P, connected tothe ground as well as between the region 24 and the substrate. Thiscapacitance can easily reach 0.1 picofarads because the gate G isseparated from the substrate only by a very small thickness ofinsulating material (a few hundreds of angstroms at the most). It is notnecessary then to add a specific capacitance to arrive at the diagram ofFIG. 2.

The resistance R may have a value of a few kilohms.

In FIGS. 3 and 4, there is also shown an N+ type diffused surface region34, laterally spaced from the diode D and connected to the ground M byan extension of the metallization 16.

Thus, between the cathode of the diode (region 12), the substrate 10 andthe region 34 there is formed an NPN type lateral bipolar transistor.This transistor makes it possible to maintain a current up to totalextinction of the overvoltage (and not only until the voltage fallsbelow the avalanche threshold V1).

What is claimed is:
 1. An integrated circuit comprising at least aterminal to be protected and a reference terminal, and means forprotecting the integrated circuit against overvoltages, said protectingmeans comprising a diode connected between said terminals, said diodecapable of being set in avalanche conduction in case an overvoltage isapplied between said terminals in a direction corresponding to a reversebias of the diode, means for modifying the distribution of equipotentiallines in a region where the avalanche conduction of the diode starts,said means connected to said terminal to be protected, and said meansbeing sensitive to the rising slope of the overvoltage, in such a waythat the avalanche triggering voltage is lower when the slope issteeper, and higher when the slope is less steep.
 2. A device accordingto claim 1, wherein the means to modify the distribution of theequipotential lines comprises an insulated gate completely surroundingthe periphery of a region diffused in a semiconducting substrate andconnected to the terminal to be protected, the gate being connected tothe terminal to be protected by means of an integrating circuit.
 3. Adevice according to claim 2, wherein the gate is connected to theterminal to be protected by a resistor and is connected to the referenceterminal by a capacitance.
 4. A device according to claim 3, wherein thecapacitance is the inherent capacitance between the gate and asemiconducting substrate separated from the gate by a thin insulatinglayer, the substrate being connected to the reference terminal.
 5. Adevice according to any of the claims 3 or 4, wherein the resistor is aregion diffused in the substrate and has a type of conductivity oppositeto the substrate.
 6. In an integrated circuit having a referenceterminal and an input terminal to be protected, a structure forprotecting the integrated circuit against overvoltages, comprising: adiode connected to the input terminal, said diode being capable of beingset in avalanche conduction in case an overvoltage is applied betweenthe input terminal and the reference terminal in a directioncorresponding to a reverse bias of said diode; and means for altering anavalanche threshold voltage of said diode, said altering means connectedto the input terminal, and said altering means responsive to a risingslope of the input voltage to lower the diode avalanche thresholdvoltage when the input voltage is rising relatively fast, and raisingthe diode avalanche threshold voltage when the input voltage is risingrelatively slowly.
 7. The structure of claim 6, wherein said diodecomprises a diffused region having a first conductivity type within asubstrate having a second conductivity type, wherein a PN junction isformed between the diffused region and the substrate.
 8. In anintegrated circuit having a reference terminal and an input terminal tobe protected, a structure for protecting the integrated circuit againstovervoltages, comprising: a diode connected to the input terminal, saiddiode formed from a diffused region, having a first conductivity type,within a substrate having a second conductivity type, and adjacent asurface thereof, wherein a PN junction is formed between the diffusedregion and the substrate, said diode further being capable of being setin avalanche conduction in case an overvoltage is applied between theinput terminal and the reference terminal in a direction correspondingto a reverse bias of said diode; and means for altering an avalanchethreshold voltage of said diode, said altering means connected to theinput terminal, and said altering means responsive to a rising slope ofthe input voltage to lower the diode avalanche threshold voltage whenthe input voltage is rising relatively fast, and raising the diodeavalanche threshold voltage when the input voltage is rising relativelyslowly, wherein said altering means is formed from a gate electrodeoverlying the PN junction adjacent to the substrate surface andseparated therefrom by an insulating layer, and an integrating circuitconnected to said gate and to the input terminal, wherein a charge onsaid gate is proportional to a change of voltage on the input terminal.9. The structure of claim 8, wherein said integrating circuit comprises:a resistor connected between the input terminal and said gate; and acapacitor connected between said gate and the reference terminal.
 10. Inan integrated circuit having a reference terminal and an input terminalto be protected, a structure for protecting the integrated circuitagainst overvoltages, comprising: a doped region having a firstconductivity type within a substrate having a second conductivity type,wherein a PN junction is formed between said doped region and thesubstrate, a portion of the PN junction extending to a surface of thesubstrate; a first conductive element connecting the doped region to theinput terminal; a gate element overlying the surface of the substrateadjacent the PN junction and separated therefrom by a thin insulatinglayer, wherein voltage applied to said gate element alters an avalanchethreshold voltage of the PN junction; a resistive element connecting theinput terminal to said gate element; and a capacitance between said gateelement and the substrate.
 11. The structure of claim 10, wherein saidcapacitance comprises capacitance which exists between said gate elementand the substrate through the thin oxide layer.
 12. The structure ofclaim 10, wherein said resistive element comprises a conductive regionof the first conductivity type formed within the substrate.
 13. Thestructure of claim 10, wherein the substrate is connected to thereference terminal.
 14. The structure of claim 13, wherein the referenceterminal is connected to the substrate through a second doped regionwithin the substrate which has the first conductivity type.
 15. Thestructure of claim 14, wherein the first conductivity type is N-type,and the second conductivity type is P-type, wherein the doped region,the substrate, and the second doped region together form an NPN bipolartransistor.
 16. The structure of claim 10, wherein said resistiveelement and said capacitance combine to form a circuit for integratingvoltages applied to the input terminal.
 17. The structure of claim 16,wherein a rapidly changing voltage in a first direction is integrated toapply a gate voltage to said gate element, and wherein the gate voltageacts to lower the avalanche threshold voltage of the PN junction. 18.The structure of claim 17, wherein a slowly changing voltage in thefirst direction is integrated to apply a lower gate voltage to said gateelement, and wherein the lower gate voltage acts to raise the avalanchethreshold voltage of the PN junction.